Field
The present disclosure relates generally to semiconductor design, and more particularly, to an engineering change order (ECO) standard cell library architecture.
Background
In chip design, an ECO is the process of inserting a logic change directly into the netlist after it has already been processed by an automatic tool. Before the chip masks are made, ECOs are usually done to save time, by avoiding the need for full ASIC logic synthesis, technology mapping, place, route, layout extraction, and timing verification. A standard cell is an integrated circuit that may be implemented with digital logic. An application-specific integrated circuit (ASIC), such as a system-on-a-chip (SoC) device, may contain thousands to millions of standard cells. An ECO standard cell is a standard cell designed for subsequent ECOs.
Traditionally, an ECO standard cell is designed by keeping fixed base layers (e.g., layers below the via zero (V0) layer, such as layers associated with front-end-of-line (FEOL) and mid-end-of-line (MEOL)). V0 and M1 layers may change based on an ECO, as those layers are programmable in a traditional ECO standard cell library. V0 and M1 layers may contribute three masks in a 14 nm manufacturing process and six masks in a 10 nm manufacturing process. Therefore, using a traditional ECO standard cell library in chip design may be expensive because of the cost associated with changing the masks for V0 and M1 layers.